This invention relates to providing a clock signal on a chip, and more particularly to a clock distribution tree on a circuit board.
Electronic circuits often operate at a selected clock rate. With each clock edge, the circuits may perform the next set of instructions, or advance to the next stage or perform some other operation, according to the design of the circuit.
Within an integrated circuit, it is desirable to have all circuits on the same chip operating on a known phase relationship to each other. Many times, it is preferred to have all circuits operate on exactly the same clock phase so that all events happen in the same time relationship to each other on the entire chip. On other circuits, it is desirable to have some events happen slightly delayed from other events so that the relative timing between the two is exactly known. In each case, knowing the exact clock timing is often important to ensure proper circuit operation.
On a semiconductor chip, when circuits are spaced apart from each other a clock signal which originates closer to one circuit than the other will arrive at the closer circuit first. Even with an electrical signal moving at the speed of light, the difference in time between when a clock signal arrives at one circuit as compared to another circuit can be significant, especially with high speed circuits now being constructed in microprocessors.
According to principles of the present invention, a circuit and method are provided for ensuring that the clock signal is uniformly provided to the entire semiconductor chip at one time. A clock signal distribution tree is provided on the support which holds the semiconductor chip. The support may be in the form of a printed circuit board, a ceramic package or some other supporting support. The support board includes very low resistance, thick metallic lines so that the clock signal travels, with very low losses and low noise to all the clock input pins on the semiconductor chip.
According to one preferred embodiment, a main clock signal is provided to the board supporting the semiconductor chip. The clock signal is output from the board to the semiconductor chip to a clock conditioning circuit. The clock conditioning circuit on the semiconductor chip amplifies the clock signal and filters out noise which may be present on the clock signal line. The clock circuit outputs the conditioned clock signal back to the board to a clock signal distribution tree. The clock signal is then distributed on the clock signal tree on the board to numerous clock signal terminals. The clock signal terminals are coupled to the semiconductor chip at clock input pads. The distance from the clock input terminal to each of the clock output terminals is identical. Accordingly, the clock signal is assured of arriving at exactly the same time at each of the clock input pads on the semiconductor chip.